With the development of communications technologies, wireless base stations begin to develop towards the directions of miniaturization, low cost, and low power consumption. Because ROC (Radio On Chip, Radio On Chip) integrates a digital part and an RF (Radio Frequency, radio frequency) part into a single chip and can greatly reduce an area of a board and a cost and power consumption of abase station, the ROC becomes one of the future developing trends of wireless base stations.
However, the ROC also introduces some new problems, that is, how to prevent interference of a digital circuit with an RF circuit and how to prevent interference between RF circuits. In the prior art, there is a method for preventing interference of a digital circuit in an ROC chip with an RF circuit. In the method, a digital multiphase clock solution is adopted to suppress interference of a digital circuit with an analog circuit. When a single-phase clock is adopted, digital circuits inside the chip basically all transit near a rising edge of the clock; therefore a great charge and discharge current exists, and a high interference pulse is produced near the rising edge. If an N-phase clock is adopted, a chip current is dispersed into clock rising edges of N different phases, and therefore energy of interference of a single clock is greatly reduced. For a wireless base station, harmful interference comes from an instantaneous high-level signal, while low-magnitude interference is submerged in background noise and therefore does not seriously affect radio communication. Therefore, by adopting the digital multiphase clock solution, the interference of the digital circuit with the analog circuit can be suppressed.
In the method for suppressing the interference of the digital circuit with the analog circuit by adopting the digital multiphase clock solution, the inventor finds that the method has at least the following problems: First, the solution is not inheritable, that is, when the scale of the digital chip increases, energy of an interference peak can be reduced only by adding a clock phase; second, when a great number of clock phases are required, a high-frequency input clock is needed, which is bad for both PLL (Phase Locked Loop, phase locked loop) selection and STA (Static Timing Analysis, static timing analysis) backend convergence; third, because in the method, a chip clock is divided into a plurality of phases, in order to prevent a problem that a requirement on interference isolation between some analog circuits in a physical layout cannot be met, clocks in a same phase need to be dispersed as much as possible in the physical layout, so that interference introduced by the clocks in the same phase to a particular location is as small as possible, and this increases design complexity of the solution; fourth, the method cannot eliminate an interference signal and can only reduce energy of an interference signal, and therefore cannot meet high requirements of radio communications indicators (such as sensitivity, a signal EVM (Error Vector Magnitude, error vector magnitude), and an ACLR (Adjacent Channel Leakage Ratio, adjacent channel leakage ratio)) in some scenarios.